1. Field of the Invention
The present invention relates to a method of crystallizing an amorphous semiconductor thin film, and a method for fabricating a poly-crystalline thin film transistor using the same, and more particularly, to a method of crystallizing an amorphous semiconductor thin film, and a method for fabricating a poly-crystalline thin film transistor using the same, in which independent two-times heat treatments are executed before and after impurities are ion-injected when a low-temperature poly-crystalline thin film transistor is fabricated via a metal induced lateral crystallization method or the other corresponding methods, to thereby shorten a heat treatment time.
2. Description of the Related Art
In general, a thin film transistor which is used in a display device such as a liquid crystal display (LCD) or an organic light emitting diode (OLED) is fabricated by processes of depositing an amorphous semiconductor thin film transistor made of semiconductor thin film on a transparent substrate such as glass or quartz, forming a gate insulation film and a gate electrode, injecting a dopant into a source and a drain, and then annealing the dopant-injected source and drain to thereby activate the injected dopant and to then form an interlayer insulation layer. An active layer (that is, a semiconductor layer) forming a source, a drain and a channel of a thin film transistor is formed by depositing an amorphous semiconductor thin film layer on a transparent substrate using a CVD (Chemical Vapor Deposition) method.
In this case, a semiconductor thin film layer directly deposited on a substrate by the CVD method and so on is an amorphous semiconductor thin film having a low electron mobility. By the way, as a display device using a thin film transistor gradually requires for a fast operating speed and becomes compact in size, a degree of integration of a driving integrated circuit (IC) becomes large and an aperture ratio of a pixel region becomes reduced. Accordingly, electron mobility on a semiconductor thin film made of silicon should be heightened so that a driving circuit is formed simultaneously together with a pixel thin film transistor (TFT), and an aperture ratio of each pixel should be heightened. For this purpose, a poly-crystallization poly-semiconductor thin film technology having higher electron mobility than that of an amorphous layer is under study.
In general, in order to obtain a poly-crystalline semiconductor thin film to be used as a semiconductor layer in a thin film transistor, an amorphous semiconductor thin film made of silicon is deposited on a substrate, and then the amorphous semiconductor thin film is heat-treated at a predetermined temperature, to thus crystallize the amorphous semiconductor thin film into a poly-crystalline semiconductor thin film. A metal induced lateral crystallization (MILC) method, a solid phase crystallization (SPC) method, and an excimer laser annealing (ELA) method can be used as the amorphous semiconductor thin film crystallization method.
Among them, the MILC method has a number of merits of having a relatively low processing temperature and a relatively short processing time as well as using a conventional heat treatment facility such as a tubular furnace.
A conventional method of fabricating a poly-crystalline thin film transistor using a MILC method will follow.
FIGS. 1A through 1E are cross-sectional views for explaining a conventional poly-crystalline thin film transistor fabrication method using a MILC method, respectively.
Referring to FIG. 1A, an amorphous silicon film is formed on an insulation substrate 10, and then the amorphous semiconductor thin film is patterned using a semiconductor layer formation mask (not shown), to thereby form a semiconductor layer 11.
Referring to FIG. 1B, a gate insulation film, and a gate electrode metal substance are sequentially deposited on the substrate, and patterned using a gate formation mask (not shown), to thereby form a gate electrode 13 and a gate insulation film 12.
Then, as shown in FIG. 1C, a photosensitive film pattern 14 slightly larger than the gate pattern is formed on the substrate 10, using an off-set mask (not shown), and a crystallization induced metal film 15 for MILC (hereinafter, referred to as a MILC metal film) such as Ni is deposited on the entire surface of the substrate.
Referring to FIG. 1D, the photosensitive film pattern 14 is removed by using a lift-off method, and thus the gate electrode 13 and off-set portions 11a and 11b in the semiconductor layer 11 are exposed. Then, high-concentration impurities are injected to form a source region 11S and a drain region 11D as shown in FIG. 1E.
Thereafter, a MILC heat treatment is performed on the substrate at a temperature between 400° C. through 600° C. under the atmosphere of an inert gas, hydrogen, or vacuum, to thereby crystallize the amorphous silicon film into a poly-crystalline silicon film. In this case, a portion contacting the metal film 15 is crystallized by a metal induced crystallization (MIC) method, and an off-set portion and a channel region 11C located below the gate insulation film which do not contact the metal film 15 are crystallized by the MILC method.
Referring to FIG. 1F, an interlayer insulation film 16 is deposited on the substrate and then contact holes 17 are formed with respect to the gate electrode 13, the source region 11S and the drain region 11D by using a contact formation mask (not shown). Then, a metal film for metal wiring is deposited and then patterned using a metal formation mask (not shown) to thereby form a metal wiring pattern 18.
As described above, in the case of the conventional thin film transistor fabrication method, a crystallization-induced metal is directly deposited on active layer, i.e., amorphous silicon film, and then heat-treated. Accordingly, a portion just below the metal deposited portion is crystallized by a MIC method which crystallizes a silicon film in which silicide made on an upper surface proceeds downwards, while a side portion where a crystallization induced metal is not deposited is crystallized by a MILC method which crystallizes the silicon in which the silicide is transferred laterally.
Here, if a crystallization induced metal remaining without reacting as silicide is included in the MIC region and the MILC region, a feature such as an increase of leakage current is deteriorated. In particular, since a crystallization induced metal is deposited on the upper portion of a source/drain region, which is near a silicon-oxide film boundary surface, which greatly influences upon a transistor feature, this feature deterioration effect becomes larger.
Meanwhile, since according to one published paper, metal pollution occurring due to a crystallization induced metal deposited on the silicon surface for the conventional MILC exists in the channel region of the poly-crystalline thin film transistor, it has been reported that a problem for deteriorating an electrical feature of a device has been known (see IEEE Trans. Electron Devices, Vol. 40, No. 5, p. 404, 1993).
Thus, in order to solve the problem, metal remaining after having formed silicide should be removed, or a crystallization induced metal should be processed so that no remaining metal exists if possible.
Meanwhile, it has been known that an amorphous silicon thin film doped with N-type impurities is generally much slower than an intrinsic silicon thin film, in view of a crystallization speed when an amorphous silicon thin film is crystallized. Thus, when an N-type poly-crystalline thin film transistor is fabricated, a heat treatment time necessary for crystallization becomes very long. Accordingly, in the case of a CMOS (Complementary Metal-Oxide Semiconductor) device where N-type and P-type thin film transistors to be widely used for a display driving IC (Integrated Circuit) exist simultaneously, a processing time becomes long and thus a processing cost increases when a poly-crystalline thin film transistor device is fabricated.
Thus, in the case of the poly-crystalline thin film transistor where N-type and P-type thin film transistors exist simultaneously, a heat treatment time necessary for crystallizing an N-type poly-crystalline thin film transistor should be shortened in order to reduce a total of heat treatment time and thus heighten a productivity.